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> Foundries and high end design companies have teams doing SRAM design.

Yep, this is also why the claim in this article title might just be a bit overstated. There's a mention that TSMC will likely announce optimized SRAM cell designs for N3-like nodes at some point, and these designs can be expected to involve some scaling.



The mention is that Wikichip expect optimized SRAM cells but there's nothing to support this. I'm not so sure given the problem they've had so far.




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