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Palomides
on Dec 15, 2022
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The Death of SRAM?
later Xeon Phi chips had this, 16GB of on-package RAM with 4x the bandwidth of the external RAM
fulafel
on Dec 15, 2022
[–]
IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4:
https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr...
(They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)
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