Not the death, but AMD's chiplets at different process nodes is the approach of the future. One of the slides I remember from an AMD presentation in recent Gamers Nexus videos showed curves for cache, logic, and a third curve across process nodes.
SRAM has desirable properties; simplicity, self sustaining state, latency.
The flattening curves follow the approach to the physical limits of doped silicon. It'll be interesting to see if another electron based but different semiconductor or another method of computing entirely (maybe photonics or some other range of the EM spectrum?) continues the rise in density or if we instead focus more on optimizing hardware and software.
Yeah, basically. The 3D-VCache approach reduces the need for scaling by increasing the surface area available. It's not quite as important to get the absolute smallest transistors if you can use a larger process node, make the cache the same size as the entire rest of the die, then stick it on top.
You're no longer competing for space on the same die as the functional units.
Their latest stacking GPU patents show the way: Stack the cache under the CPU, not above it. The cache chips themselves do not produce much heat (as a process optimized for cache will be very low leakage, and only small areas of the cache are actively switching at any given moment), the problem with current stacked products is that the cache is between the active die and the heatsink.
The reason they didn't do it in the right order to start with is that the top die cannot be designed to work both with and without the cache. They can only start stacking the cache below the cpu once they accept that every single product will have a stacked cache.
Couldn't they make a "dummy" die for non-cache products? Basically the only features on the die would be whatever through vias were necessary; I'd assume this could be done on with comparatively old/cheap/debugged processes and have an extremely high yield.
AIUI AMD's commercial V-Cache chips are slightly lower max clock speed than comparable chips without V-Cache, and thermals are probably why. It's still a huge win for most applications, nonetheless.
Rumor has it the 7000-series X3D chips that are coming down the line aren't going to be down-clocked relative to their non-X3D counterparts. Maybe they're undervolting or just better binned? I guess we'll find out shortly.
According to TechPowerUp, they’ve solved the heat dissipation problem for this gen in a different way:
> These would use one or two "Zen 4" chiplets with stacked 3D Vertical Cache memory. A large amount of cache memory operating at the same speed as the on-die L3 cache, is made contiguous with it and stacked on top of the region of the CCD (chiplet) that has the L3 cache, while the region with the CPU cores has structural silicon that conveys heat to the surface
SRAM has desirable properties; simplicity, self sustaining state, latency.
The flattening curves follow the approach to the physical limits of doped silicon. It'll be interesting to see if another electron based but different semiconductor or another method of computing entirely (maybe photonics or some other range of the EM spectrum?) continues the rise in density or if we instead focus more on optimizing hardware and software.