Fantastic article: "About 50% of the chips worked, so he examined the rejects individually with tweezers to figure out what adjustments would improve the yield."
With tweezers. And they sent these same ICs into space, if I read correctly. Nowadays, due to the miniaturization, you can get bitflips or energy spikes when cosmic radiation particles hit your ASICs. I've worked at SRON, the Dutch space agency, and remember a team down the hall working on radiation-hardened ASICs. The team worked to mitigate these risks with ground plates and other stuff inside the ASICs.
Strictly SOS was more theory than practice. I sounds really good on paper. In manufactured practice it has major problems.
Bulk CMOS was largely adopted in the late 1980s by DOD and used ever since. The ONLY source for SOS was RCA and they shortly after that shutdown their process lines. Mostly because the sapphire interface with the bulk similar caused even more physical and radiation problems that it solved. I was involved in the final RCA SOS parts proposed for military use (I was the contract validator/monitor) and they got their asses handed to them by a bulk CMOS proposal from a well known company. That was all she wrote on SOS.
Rule of Thumb: interfaces between materials are where all problems of quality and reliability start! Electrical noise comes from interfaces. Failure mechanisms in MOSFETs comes from interfaces. Physical failure comes from interfaces. So the more interfaces you insert into anything manufactured, the more problems it will have.
Hence "Bulk CMOS" ultimately became the standard for rad hard parts. Bulk CMOS is also what the most commercially economic CMOS is made from. So double win. There are things you have to do in the design and process to improve rad hardness but the baseline process should be as simple as possible.
One of those problems is the lattice constant difference between sapphire and silicon is too large and creates the one thing you never want with radiation: dangling bonds or capped but susceptible bonds that can be irradiated into being dangling. Those dangling bonds can be neutral or charged. When neutral they can become charged by normal currents.
The lattice mismatch also created physical problems where the sapphire could and would pop-off the silicon substrate during temperature excursions typically seen in space applications. Not good.
With tweezers. And they sent these same ICs into space, if I read correctly. Nowadays, due to the miniaturization, you can get bitflips or energy spikes when cosmic radiation particles hit your ASICs. I've worked at SRON, the Dutch space agency, and remember a team down the hall working on radiation-hardened ASICs. The team worked to mitigate these risks with ground plates and other stuff inside the ASICs.