I don't think that's true either. You can get 8-core desktop Ryzen parts that have a TDP of 65 watts. I have a passively cooled 8-core Ryzen system that uses a 240 watt power supply.
Also: by the time you've wired up 8 raspis you end up using quite a bit of power just to connect them all together with a switch.
Raspberry Pi 4s need a maximum of 15 watts each. So 120 watts just for the computers. Even if you discount the power consumption of the switch, my 240 watt Ryzen computer is still going to beat that joule-for-joule.
Edit: one more thing, that 240 watt system also powers a 75 watt GPU, so it's definitely more wattage than really required for the CPU alone.
You're calculating the raspi 4 power consumption based off of recommended USB power supply current rating. The actual expected load power consumption without peripherals is 1/5 to 1/3 of that (3-5 W rather than 15 W).
static to dynamic power ratio isn't efficiency though (and static power in modern desktop chips is tiny compared to the dynamic power). The dynamic power is not linearly related to processing speed (in fact it's much worse). If you downclock and undervolt a ryzen processor it will use much less power than the decrease in speed (e.g. from stock, if you drop performance by ~20% you might get a ~40% power decrease). Obviously at a certain point you will start to get worse again but most chips are not at peak performance/watt at their stock settings because raw performance and performance/cost also matters.
That scaling has a limited range before static power becomes dominant. Compute efficiency is compute / energy (total power * time). Total power includes static power. An SBC pulls far less from the wall than an x86 desktop could ever hope to when calculating the first million digits of pi.
As an example: even if I halted my desktop at 0 MHz and it still magically took the same time to calculate the first million digits of pi as a raspberry pi, it still would be using far more power.
Static power ratio is increasing in modern processing nodes, to the point where a "rush to idle state" strategy starts to make sense because you can power down subsystems in idle states but you can't do that if you lower processing speed. The tradeoff would of course be different in a chip that was architecturally designed from the ground up for low-performance use, but that would be from things other than just a lower frequency for the same chip.
